1. Field of the Invention
This invention relates to oscillators, and more particularly, to a high-frequency ring oscillator which is constructed from a ring of cascaded delay circuits each being implemented from a CMOS (complementary metal-oxide semiconductor) inverter incorporated with either a positive-feedback gate structure or a positive-feedback drain structure so as to improve the output-to-output characteristics of the ring oscillator.
2. Description of the Related Art
A ring oscillator is a circuit that includes a ring of cascaded delay circuits, such as a ring of cascaded inverters, for generating an oscillating signal at a frequency proportional to the magnitude of a control voltage. The overall feedback gain of the cascaded delay circuits should be greater than 1 and inverted in phase. Assume the total number of the cascaded delay circuits is n.
If n is very large or the operating frequency is very low, the ring oscillator will operate in a delayed oscillation mode. In this mode, the output frequency f.sub.OSC of the ring oscillator is as follows: EQU F.sub.OSC =1/[n.multidot.(t.sub.pHL +t.sub.pHL)]
where (t.sub.pLH +t.sub.pHL) is the delay time in each of the cascaded delay circuits.
On the other hand, if n is small and the operating frequency is high, the ring oscillator will operate in a phase-shifting sinusoidal oscillation mode. In this mode, the output angular frequency .omega..sub.OSC (where .omega..sub.OCS =2.pi.f.sub.OSC) of the ring oscillator will comply with the following Nyquist criteria:
.vertline..beta.A(.omega..sub.OSC).vertline.=1 EQU .theta.(.omega..sub.OSC)=180.degree.
where
.beta. is the feedback factor; PA1 .beta.A is loop gain; and PA1 .theta. is phase shift. PA1 V.sub.id is input differential voltage; PA1 g.sub.m N1 is the transconductance of the NMOS transistor N1; PA1 g.sub.m N2 is the transconductance of the NMOS transistor N2; PA1 V.sub.GS N1 is bias to the NMOS transistor N1; PA1 V.sub.tN1 is the threshold voltage of the NMOS transistor N1; PA1 .mu..sub.N is the carrier mobility of the NMOS transistor; PA1 Cox is the unit gate capacitance of the NMOS transistor; PA1 .lambda. is the channel modulation constant; and PA1 t.sub.p is the main extreme time constant. PA1 (1) First, it can be seen that the drain-to-source current I.sub.DS N3 of the NMOS transistor N3 decreases as the control voltage V.sub.ctl at the gate of the NMOS transistor N3 is decreased. However, the 45-degree phase-shift frequency f.sub.-3dB increases with the current I.sub.DS N3. This is because that as the current I.sub.DS N3 decreases, it causes the channel capacitance of the PMOS transistor working in the linear region to be reduced. Moreover the rate of change of the channel capacitance is faster than that of the transconductance. PA1 (2) Second, as the current I.sub.DS N3 decreases, it causes the gain to decrease as well, thus decreasing the amplitude of the output frequency of the ring oscillator. Therefore, the ring oscillator is unable to operate when the control voltage falls below a certain level to generate a low frequency output. PA1 (3) Third, when the control voltage V.sub.ctl is below 1.2 V, the gain is reduced to below 1, which does meet application requirements.
Since .beta.=1, the ring oscillator should be designed in such a manner that A.gtoreq.1 and .theta.=180.degree./n. The provision of A.gtoreq.1 ensures that the ring oscillator can output an oscillating signal. However, if A&gt;1, it will cause the remaining oscillating signal to continuously increase in amplitude until reaching the top and bottom nonlinear regions. In these regions, both the gain and the bandwidth will decrease, causing the oscillating signal to be somewhat distorted in waveform. However, in these regions, the operating mode of the ring oscillator will be close to the delayed oscillation mode, causing the output frequency of the oscillating signal to be decreased slightly. Therefore, the gain should not be designed to be overly large.
The delay circuits used in the ring oscillator are best implemented from common source logic (CSL) circuits, such as CSL inverters. A CSL circuit is a differential-type of amplifier. As mentioned above, the CSL circuit should not be overly large in gain near the low-frequency region in order to allow the ring oscillator to generate the highest possible frequency.
In high-frequency ring oscillators of more than 1 GHz, since they typically include a lesser number of delay circuits, the output frequency is sinusoidal in waveform rather than a full-swing square waveform. In the case of a 4-stage ring oscillator, for example, the delay circuits are each operated in such a manner that the absolute value of the gain is greater than 1 i.e., .vertline.A.vertline.&gt;1) for each phase shift of 45.degree.. However, when operating under a low working voltage, since the common current source cannot be kept in the saturation mode all the time, the common-mode gain will become the primary factor that affects the output frequency. Therefore, under this condition, the output frequency of the voltage controlled oscillator (VCO) is not be adjusted in a linear manner with the magnitude of the control current.
FIG. 1 is a schematic block diagram of a conventional 4-stage ring oscillator. As shown, this conventional ring oscillator includes four cascaded stages of CSL inverters 10, 20, 30, 40, a first CSL buffer 50, a second CSL buffer 60, and a CSL divide-by-2 divider 70. The four CSL inverters 10, 20, 30, 40 are all identical in function and structure as illustrated in FIG. 2.
The CSL inverter of FIG. 2 is symmetrical in CMOS configuration, including PMOS transistors P1, P2, and NMOS transistors N1, N2, N3. Further, the CMOS CSL inverter has a positive input port 310, a negative input port 320, a positive outlet port 330, and a negative outlet port 340. A control voltage V.sub.ctl is applied to the gate of the NMOS transistor N3. Assume body effect is neglected, then the gain Av and 45-degree phase-shift frequency f.sub.-3dB of the CMOS CSL inverter of FIG. 2 can be formulated as follows: ##EQU1## where V.sub.od is output differential voltage;
Assume the 0.5.mu.5.0V2p3m CSL inverter manufactured by the TSMC (Taiwan Semiconductor Manufacture Corporation) of Taiwan is used to serve as each of the CSL inverters in the ring oscillator of FIG. 1. Assume the common-mode voltage V.sub.CM at the differential input of the CSL inverter is V.sub.CM =1.2 V (which serves as a DC bias to the CSL inverter). Then, with the first and second CSL buffers 50, 60 and the CSL divide-by-2 divider 80 serving as a load to the cascaded CSL inverters 10, 20, 30, 40, the simulated results of the gain and 45-degree phase-shift frequency f.sub.-3dB are shown in the following Table 1.
TABLE 1 ______________________________________ V.sub.ctl (volt) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 ______________________________________ Av (times) 1.20 1.16 1.1 1.014 0.884 -- -- f.sub.-3dB (GHz) 1.35 1.36 1.37 1.39 1.40 -- -- I.sub.DS N3 (.mu.A) 235 219 198 172 135 -- -- ______________________________________
From the data shown in Table 1, it can be learned that the prior art of FIGS. 1-2 has the following drawbacks.
Due to the foregoing drawbacks, the conventional ring oscillator is inoperable when the control voltage is reduced to lower than 1.2 V, at which point the gain is reduced to below 1.